微波电路经验法则100~110

For a given microstrip or stripline geometry, the filling factor is very nearly a constant versus the value of the dielectric constant of the substrate. The inductance per length does not change versus the dielectric constant of the substrate, only the capacitance/length does.对于给定的微带或带状线形状，填充系数几乎是不随截止的介电常数的变化。单位长度的电感量并不随衬底的介电常数变化，仅单位长度的电容量会随介电常数变化。

For ideal coplanar waveguide (with very thick substrate and no ground plane on the back side, thin, perfect conductors), filling factor is 50%. Therefore the Keff is equal to:
Keff=(ER+1)/2 
This is the average value of air (ER=1) and the substrate.对于理想的共面波导（衬底介质足够厚、背部没有地平面、极薄的理想导体），填充系数为50%，则有效介电常数Keff为：

Keff=(ER+1)/2
即空气和衬底介电常数的平均值。

The side dimension of a cube corner reflector is ideally greater than 10 wavelengths of the signal you are trying to reflect. Any comments are appreciated!角反射器的侧边尺寸理想情况下大于10倍被反射信号的波长。欢迎评论。

The effect of surface roughness on microstrip lines is a gradual degradation in attenuation due to conductor loss. If RMS roughness is on the order of one skin depth, conductor attenuation (alpha-c) is increased by 60%. If surface roughness is much more than one skin depth, the increase is 100% (2X ideal loss).微带线表面粗糙度的影响是导体损耗逐渐增大，如果均方根（RMS）粗糙度约为一倍趋肤深度量级，则导体损耗（alpha常数）增加60%，如果粗糙度远大于一倍趋肤深度，则导体损耗增加100%（即理想损耗的2倍）。

We finally have a rule of thumb for the equivalent electrical length of a microstrip mitered bend. The "extra" length is equal to half the width of the line. It is explained here. Thanks to Kevin!一个微带线切角转弯的等效电长度约为线宽的一半。

You should plan on the off-state resistance to somewhere between 5000 ohm-mm and 50,000 ohm-mm. In most designs you can just ignore it, but in this example, it's important.（射频开关）关断状态的阻值（电阻率）大概在5000~50000Ω·mm，绝大多数设计中都可以忽略，但在这个例子中不行，很重要！

The minimum size for a gate choke resistor is on the order of 500 ohms. Many designers use thousands of ohms, this merely slows down the switch. The gate is already (at least partially) decoupled from the RF without the resistor! Some day we'll add an analysis to back up this bold statement... For very high speed, you can eliminate the gate choke resistor by using a low impedance bias network (quarterwave stub terminated in a capacitor for example).栅极隔离电阻的最小值大概是500Ω，很多设计师都采用数kΩ的电阻，这仅仅会减慢开关的速度（而并没有太多其他好处）。即便没有隔离电阻，栅极已经是（至少部分是）跟射频信号隔离的。对于极高速的开关，可以通过采用低阻偏置网络（例如端接电容的1/4波长线）来去除栅极隔离电阻。

If you want to simulate rectangular coax with a linear simulator such as Microwave Office or ADS, you can model it quite accurately as a round coax line, subject to one condition described here. Just compute the equivalent cross-sectional area of the center conductor and divide it by pi to get the diameter of an equivalent coax. Set the outer conductor to whatever you need to get the impedance you want (generally 50 ohms).如果你想用诸如Microwave Office 或 ADS之类的线性仿真器来仿矩形同轴线，用圆形同轴线来模拟仍然很精确，只有一个前提条件：计算一下内导体的等效截面积，再除以π就得到等效同轴线的直径。通过改变外导体直径获得你期望的阻抗（通常是50Ω）。

Regarding RMS transmission phase errors in a solid state power amp (SSPA), the "phase efficiency" is approximated simply as the cosine squared of the RMS phase error of the amplifiers. Thus if your RMS phase error is 45 degrees (which really sucks) your phase efficiency is 50% and you are losing half of your power into isolation loads (-3.01 dB below what is possible). In order to hit 99% phase efficiency your amplifiers need to be phased to 5.74 degrees RMS. In the case of a two-way combiner, the peak error is twice the RMS error, so your amplifiers must be within 11.5 degrees transmission phase.关于固态功放的RMS传输相位误差，“相位效率”大概是放大器RMS相位误差余弦值的平方。如果你的RMS相位误差是45deg（很烂），则相位效率是50%，有一半的功率损失在隔离负载上（比最大可能功率低3dB）。想要获得99%的相位效率，则放大器的相位误差必须小于5.74deg RMS，对于一个两路的功率合成器，峰值误差是RMS误差的两倍，因此放大器的传输相位差必须小于11.5deg。

Following rule 110, suppose you pick amplifiers from the "Waffle Pak of Uniformly Distributed Phase", or WPUDP, spanning X degrees (more specifically, WPUDP-X). The expected RMS phase error is X divided by the square-root of twelve. You should recognize that term as the square root of the variance (σ, not σ2 which is the variance) of a uniform distribution, something that should be covered in Six Sigma training but is usually omitted to make the course so easy that an imbecile can become a "black belt." So, if your amplifiers are uniformly spread over 90 degrees, your RMS error is expected to be 26.0 degrees, and you should see 80.8% phase efficiency (-0.93 dB below what is possible). Of course, basing this calculation on just the waffle pak distribution ignores phase tolerance contributions of wirebonds and combiners, you are on your own to estimate these and recalculate the phase distribution. If you don't understand (and memorize) rules 110 and 111, you might want to pick a different career other than SSPAs....接上条，假设你从相位均匀分布的晶圆批（下称WPUDP）中挑选放大器，相位分布区间X deg（下称WPUDP-X），期望的RMS相位误差是X除以12的平方根。你应该把X项看作是一个均匀分布的方差的平方根（σ, 而不是方差 σ2 ），这本是6-σ培训课程应该介绍的内容，但通常为了使课程简单到连白痴也可以达到“黑带”段位而被省略了。因此如果你放大器相位误差在90deg范围内均匀分布，则你的RMS相位误差期望值是26deg，大概是80.8%的相位效率（比最大可能值低0.93dB）。当然，以上计算仅考虑晶圆分布，而忽略了键合线和合成器相位容差的贡献，你需要自己去考虑这些因素再重新计算相位分布。如果你看不懂本条和下条经验法则，那么也许你可以考虑换个不是固态功放的职位……